1. Field of the Invention
The present invention relates to digital image processing technologies, and more particularly to effective technologies for a compressed image data decoder.
2. Description of the Related Art
Conventional technology in this field will be described with reference to FIG. 2B. A conventional image output apparatus 1 formats image data synchronously with a system clock sclk 5 and horizontal and vertical sync signals of a display device such as a CRT, and outputs the formatted image data. Since the image output apparatus 1 outputs image data of a predetermined format at a predetermined timing, an external data buffer 2 for temporarily storing the image data outputted from the image output apparatus 1 is required if a host controller 4 such as a microprocessor executes a so-called direct memory access (DMA) transfer. Upon reception of a data request host req signal from the microprocessor 4, the image data is asynchronously outputted from an output terminal data out 4' of the data buffer 2.
The conventional technology described with reference to FIG. 2B has been found, however, unsatisfactory because the data buffer 2 is required to be provided externally between the image output apparatus 1 and microprocessor 4. This data buffer 2 is required to have a memory capacity sufficient for the maximum amount of data per one DMA transfer. For example, the data buffer 2 is required to have a capacity of 352.times.3 pixels.times.2 per one line of RGB. Therefore, the amount of hardware increases.